1. Technical Field
The present invention relates to a semiconductor package and a manufacturing method thereof.
2. Description of the Related Art
A semi conductor package is manufactured by forming a metal post and an insulating layer on a semiconductor substrate, of which one surface is formed with an electrode, like a wafer level package (WLP) and a chip scale package (CSP).
In such semiconductor package, an outer-layer circuit is formed on the metal post, and a solder is formed on the outer-layer circuit, in order to make an electrical connection with an external device such as a main board.
In such conventional art, a via is formed to penetrate through the semiconductor substrate in order to utilize both surfaces of the semiconductor substrate. The via, however, is formed by a separate process from the metal post and then is coupled to the metal post, thereby lowering the reliability of the coupling between the metal post and the via, adding the manufacturing processes and increasing the manufacturing cost.